Serial data communications are used to communicate data between many types of devices. Receiving and correctly decoding a stream of serial data requires the transmitting and receiving devices to be synchronized. Often, communicating a separate clock signal in addition to a stream of serial data to the receiving device is inefficient or impractical. Instead, the receiving device can perform clock data recovery techniques using a phase locked loop (PLL). The PLL analyzes the serial data stream to synchronize the receiving device.
However, PLLs often increase the cost and complexity of the receiving device. This is especially true for high-speed serial data communications, which require specialized PLLs capable of analyzing a high-speed serial data stream. To overcome these difficulties, some serial data recovery techniques do not require clock data recovery. These serial data recovery techniques do not require a specialized PLL, thereby reducing the cost and complexity of the receiving device.
Unfortunately, serial data recovery techniques that do not require clock data recovery typically have a low jitter tolerance. Jitter is small random variations in the timing of the serial data signal. For example, a typical prior serial data recovery technique has a jitter tolerance of +/−0.25 UI. Because the jitter introduced by the transmitting and receiving devices may be as much as 0.20 UI, the actual remaining jitter tolerance may be as little as 0.10 UI. This jitter tolerance is too small for many serial data communication standards, such as ASI.
Additionally, many serial data recovery techniques require the receiving device to operate at a clock speed greater than or equal to the serial data rate. The high operating speed requirements for high-speed serial data communications applications are impractical or impossible to satisfy for many types of receiving devices.
It is therefore desirable for a system and method to receive and decode serial data communications without performing clock data recovery. It is further desirable for the system and method to have a high jitter tolerance. It is also desirable for the system and method to be implemented in a receiving device having a clock speed less than the serial data rate. It is also desirable for the system and method to be optimized either for increased serial data rates or for increased jitter tolerance.